The present invention relates to a clock routing circuit for routing two different clock signals in a glitch-less manner.
The timing of events is key to proper processing within integrated circuits, such as user-defined logic devices. Accordingly, a single clock is typically used as a reference to determine the timing of events. Each process may be clocked from a single distributed clock signal, providing highly synchronized processing.
However, not all processes are active at all times. Therefore, some processes do not require a continuous clock signal. Continuously providing the primary clock signal to a process that does not require such adds unnecessarily to the power consumption of the chip. A significant cause of power consumption within a user-defined logic device is the power required to distribute the primary clock signal throughout the chip.
To lessen this power consumption, some users of user-defined logic devices utilize a portion of the resources of the logic device to route a secondary clock signal in place of the primary clock signal, wherein the secondary clock signal has a frequency much less than the frequency of the primary clock signal. Routing the secondary clock signal enables the user-defined logic device to enter a low power xe2x80x9csleepxe2x80x9d state. Because the power consumed when providing a low frequency clock signal to a process is less than the power consumed when providing a high frequency clock signal to the process, the power consumption of the chip is reduced. To further reduce power consumption, some user-defined logic devices are capable of gating, or preventing the routing of, the primary clock signal. One such clock gating circuit is described by Alfke et al. in commonly owned, co-pending U.S. patent application Ser. No. 09/336,357, filed Jun. 18, 1999.
In addition, some integrated circuit chips must be capable of operating in response to two separate clock signals. For example, integrated circuits that operate in accordance with the proposed PCI-X bus interface standard must be able to operate in response to both a 133 MHz clock signal and a 66 MHz clock signal. That is, a PCI-X bus interface will typically operate in response to a 133 MHz clock signal, but must be backward compatible to operate in response to a 66 MHz clock signal.
A 2-to-1 multiplexer can be used to selectively route one of a primary clock signal and a secondary clock signal (or no clock signal). In this structure, the input terminals of the 2-to-1 multiplexer are coupled to receive the primary and secondary clock signals, and the output terminal of the multiplexer provides the selected clock signal. However, switching from one clock signal to the other can yield undesirable effects including glitches and runt pulses in the routed clock signal. In the present disclosure, a glitch or runt pulse is defined as a pulse having a width that is less than the width of the smaller of the primary or secondary clock signal.
It would therefore be desirable to have a clock routing circuit that eliminates undesirable clock signal disturbances, such as glitches and runt pulses.
Accordingly, the present invention provides a clock routing circuit that is coupled to receive a primary clock signal, a secondary clock signal, and a select signal. When the select signal is in a first state, the clock routing circuit passes the primary clock signal as an output clock signal. When the select signal transitions to a second state, the clock routing circuit waits for the primary clock signal to transition in a predetermined direction (i.e., rising edge or falling edge). Upon detecting the transition of the primary clock signal, the clock routing circuit holds the state of the output clock signal. The clock routing circuit then waits for the secondary clock signal to transition in the predetermined direction. Upon detecting the transition of the secondary clock signal, the clock routing circuit passes the secondary clock signal as the output clock signal. By sequencing the transition between the primary clock signal and the secondary clock signal in this manner, clock signal disturbances are eliminated.
In one embodiment of the present invention, the primary and secondary clock signals are asynchronous. In another embodiment, the secondary clock signal can be replaced with a signal having a constant value. In yet another embodiment of the present invention, the predetermined direction can be selected by the user of the clock routing circuit. By selecting the predetermined direction to correspond with a rising edge, the output clock signal will have a logic high value when in transition. Conversely, by selecting the predetermined direction to correspond with a falling edge, the output clock signal will have a logic low value when in transition.
In another embodiment, when the select signal is in a first state, the clock routing circuit passes the primary clock signal as an output clock signal. When the select signal transitions to a second state, the clock routing circuit waits for the primary clock signal to reach a predetermined logic state. When the primary clock signal reaches the predetermined logic state, the primary clock signal is prevented from being passed as the output clock signal. At this time, a keeper circuit maintains the output clock signal at the predetermined logic state.
The primary clock signal may be in the predetermined logic state when the select signal transitions to the second state. In this case, the primary clock signal is immediately prevented from being passed as the output clock signal. Advantageously, there is no need to wait for a transition of the primary clock signal in this case.
The next time that the secondary clock signal transitions to the predetermined logic state, the clock routing circuit passes the secondary clock signal as the output clock signal. Because the keeper circuit is holding the output clock signal at the predetermined logic state at this time, there are no glitches in the output clock signal. Under worst case conditions, the time required to switch the output clock signal from the primary clock signal to the secondary clock signal is equal to one half cycle of the primary clock signal plus one cycle of the secondary clock signal. The output clock signal can be switched from the secondary clock signal to the primary clock signal in a similar manner.
The present invention also includes a control signal that can be asserted to maintain the source of the output clock signal, regardless of the state of the select signal.
The present invention will be more fully understood in view of the following description and drawings.